AMD 24 Day was held at the University of Standford University seminar Hot Chip 21, revealed the code-named Magny-Cours the 12-core processor micro-architecture design, will use the Multi-Chip Package Technology, the two six-core encapsulated in the same processor, the same time, improve memory broadcasting technology to reduce the memory latency to happen.
AMD Senior Fellow Pat Conway pointed out that the micro-architecture will soon be in 2010 the 12-core Opteron processor launch Magny-Cours will adopt 45nm process, which is composed of two six-core Istanbul and through the Multi-Chip Package Technology encapsulated in the with a processor, the situation is the same as the Intel Core 2 Quad, but the difference is that the core Magny-Cours 2 is used Hyper-Transport 3.0 protocol directly connected without the need to use FSB technology, like Intel, in the middle to pass North Bridge chip significantly raised the delay values.
As the process advances to the single-core Socket support 12, so 4 Way system will provide a powerful 48-core computing power, in the same volume of computing power will dramatically increase the next double.
Micro-architecture design, Magny-Cours is still based on the existing K10 micro-architecture, each one has a 6 Die core, each core has 512KB L2 Cache stars and share 6MB L3 Cache, and then connect through the Hyper-Transport Ports core of another one. In addition, Magny-Cours Support HT Assist technology, processors, memory addressing information can be stored in L3 Cache in, or about 1MB memory space, storage, memory system, addressing information, which will reduce the memory system delays from 120ns to reduce to only 50ns, but the L3 Cache size reduction will have the opportunity to reduce the hit rate, but Pat Conway said the HT Assist on the hit rate is not obvious.
Finally, Pat Conway said it will add a similar Opteron processors Intel Hyper-Threading technology, but the effect would be further strengthened, I believe will appear in next-generation micro-architecture Bulldozer.