"Optimizing SHA-1 Hash Function for High Throughput with a Partial Unrolling Study", Integrated Circuit and System Design, 2005
- the throughput : about 3,000 Mbps
 "Throughput Optimized SHA-1 Architecture Using Unfolding Transformation", Application-specific Systems, Architectures and Processors, 2006. ASAP '06.
- According to the results of FPGA implementations, 3,541 Mbps with a pipeline
- synthesis results using 0.18mum CMOS technology showed that 10.4 Gbps with a pipeline
3,541 Mbps = 22M/sec
10.4 Gbps = 65M/sec