Bitslice DES for AVX / XOP


AMD-XOP Enhanced Bitslice DES

What is this?

To introduce the 32nm process generation AMD K11 (Bulldozer) instruction set extensions supported by microarchitectureXOPis, vpcmov instruction that will be added. This is in AltiVec vsel, Cell BE SPE in the same selb and select operations is to achieve 3-bit input. As an implementation of AltiVec and SPE, and by using it, Bitslice DES reduce the number of gates can be expected to configure the logic operation.

AVX version 3 of the SIMD operands by using a logical instruction bit extra instruction while reducing MOVDQA further by reducing the number of VPCMOV logical operation can be a greater density of the operation.


Public Notes 2 clause BSD-style license applies. Multiple licenses are unlikely because we do not demand too much current. Freely available for license.


Only here do we only focused on the optimization reduces the number of bit logical operation only. The operation reflects not the actual throughput. Traditional Bitslice DES might cause more degradation. Please think about reference only.


Version of the old specification (SSE5)

No comments:

Post a Comment