Enhanced Bitslice DES

http://dango.chu.jp/hiki/?Enhanced+Bitslice+DES#googtrans/ja/en

Specific type of logical operations that support 3 Bitslice DES input

Logical instruction to take advantage of three input bits

Matthew Kwan's code is a sequence using only two inputs strictly logical instruction, SIMD instruction set architecture as part of a type, MUX select input bit SELB or considered as three-(3-source bitwise select ) is to support instruction. Languages like C and expressed

D = (A & ~ C) | (B & C); 

Be.

MUX as instruction set architecture to support instruction, will include the following.

• VMX / AltiVec (PowerPC; IBM / Freescale)
• SSE5 (AMD64; AMD)
• NEON (ARMv7; ARM)
• SPU ISA (Cell BE SPE; IBM / Sony / Toshiba)

3 with two input logical operators because it can not be a single instruction takes four instructions, use no hands.

Mark Bevandpreceded by Mr. Cell has been created for the implementation, the exact mechanism that generates recursive +-robin selects the best and I think there are so many applications have influence some versatility.

Us is, MUX with an order to reduce gate count, by doing more aggressive, less than an average of 40 gates (Cell BE SPU) was achieved. Cell and for the implementation of AltiVec, Matthew Kwan 1 overall in comparison with those so that's through about 20% performance improvement.

Comparison of S-box gates

	S1	S2	S3	S4	S5	S6	S7	S8	Average	Remarks
sboxes.c (M. Kwan)	63	56	57	42	62	57	57	54	56.0	standard gate
nonstd.c (M. Kwan)	56	Fifty	53	39	56	53	51	Fifty	51.0	non-standard gate
best.c (M. Bevand)	Fifty	46	46	34	Fifty	47	46	45	45.5	SPU (Cell BE)
sboxes-alti.c	45	42	43	The 32	44	43	42	41	41.5	AltiVec (PowerPC)
sboxes-spu.c	44	41	41	Thirty	42	41	Forty	Forty	39.9	SPU (Cell BE)

Download

Cell SPU and AltiVec we do the optimization version of the distribution-specific. The GNU GPL and BSD-style dual-licensed.

4th Edition (Updated 2009.01.02)

Archive version and another separate SPU AltiVec version.

For AltiVec version is that the algorithm can reduce the gate S2 2 function generator. About SPU version, fine tune the code, S4 third argument passed to the function by doing a spu_xor → spu_eqv, a3, and I'll give you a bit reversal Nearby x1 = a3, so that we can save one instruction.

• For PowerPC AltiVec VMX　
  • BSD-style licensed
  • GNU GPL version

• Cell BE SPU (SPE) for
  • BSD-style licensed
  • GNU GPL version

• For AMD SSE5
  • →Bitslice DES and SSE5

If there is a wish other licensingplease contact us.

Enhanced Bitslice DES using the software

• Vectripper by Mr. Tmkk
  • The core AltiVec routine for me (sboxes-alti.c) has been used (as of December 27, 2008)

DES bitslice

DES Bitslice - http://dango.chu.jp/hiki/?Bitslice+DES#googtrans/ja/en

Bitslice DES is - make the throughput by parallel processing
Mechanism
DES depth discussion about implementing such software, please refer to the following sites.
Http://Ruffnex.oc.to/Kenji/Xrea/Des.txt (Aiko from Kenji's site)
Where DES is the most time eating the "encryption operation 16-stage" is represented by the loop. Processing time in the implementation is fully optimized for more than 90% of the total. UFC and libdes libraries, such as expanding the inverted S-Box · Gather references to conduct that reduce transposition tables, improving performance and reducing the number of memory references.
The opposite idea, but once that process in making a performance by processing multiple data in parallel Bitslice DES is slower. n n-bit processor machine assumes a 1-bit vector in parallel, run together. Currently, most modern CPU is 64bit or 32bit processor so, the 32 parallel, and can not run in parallel, or 64.
The problem in this parallel processing on Table S-BOX is called random. Reference to the table, each reconstructed block of 6 bits, since it is necessary to disassemble again.
S-BOX takes the input as 06-bit 64-bit output is 0 to 4 and 15. That would implement a combination of all input and output bit Boolean bit operations for this table is equivalent to reducing significantly the cost to reconstruct the sequence each time, DES register bit width of all the loop processing core not be implemented in parallel computing is a few minutes.
Cryptographer Eli Biham is an Israeli professor of this algorithm, DES for a modern high-speed RISC announced parallel implementations.
Improvements have been made repeatedly to reduce the number of bit logical operation, is currently implementing many of Mr. Matthew Kwan has said RISC processors as the best.
http://www.darkside.com.au/bitslice/

Application of SIMD instructions
For Intel x86 MMX / SSE * and PowerPC AltiVec (VMX) can be regarded as parallel machines and 128 not parallel 64. 64bit or 32bit general purpose registers that are only minutes parallelism, 64bit or 128bit SIMD can be operated in parallel or replace an order, you can calculate faster.
An Implementation of Bitsliced DES on the Pentium MMX Processor
http://www.engr.uconn.edu/ ~ zshi/course/cse5095/ref/yhilewitz_thesis.pdf

UNIX crypt and its application to parallel computing 2ch Trip
Since the UNIX crypt is an application of DES, Bitslice DES can still use the algorithms. UNIX crypt Bitslice DES algorithm was applied to the crack of the software as John the Ripper is well known.
Trip search program for Windows is also Tripcode Explorer Matthew Kwan's S-box based Bitslice DES algorithm is used.

Enhanced Bitslice DES - to support the implementation of logical operations-focused three-input
Moved to a separate page
*Cell SPU / Altivec for Enhanced Bitslice DES(http://dango.chu.jp/hiki/?Enhanced+Bitslice+DES#googtrans/ja/en)
*AVX + AMD XOP (VPCMOV) for Bitslice DES for AVX / XOP(http://dango.chu.jp/hiki/?Bitslice+XOP#googtrans/ja/en)
*AMD SSE5 (PCMOV) for DES Bitslice and SSE5(obsolete)(http://dango.chu.jp/hiki/?SSE5+and+Bitslice+DES#googtrans/ja/en)

Oracle password algorithm

[Oracle 7-10g]
Password rule : alphanumeric and $,%,_, max 30 character

DES-CBC ( ID || Password || zero-padding , key=0x0123456789ABCDEF , IV=all zero)
ref) The next level of Oracle attacks (http://freeworld.thc.org/papers/thc-orakelsniffert.pdf)

[Oracle 11g]
SHA-1( password || salt )

[etc]
Oracle 9i TNS 3DES authentication details
Oracle 10g TNS AES-128 authentication details
Oracle 11g TNS AES-192 authentication details

[speed]
700,000 pass/sec
http://www.red-database-security.com/whitepaper/oracle_password_cracker.html
http://www.password-crackers.com/en/category_121/